1. Field
The present invention relates to a CDMA receiving apparatus and CDMA receiving method, for use in a CDMA communication system, that receive a signal generated by spreading a transmitted data sequence with a spreading code sequence, and after converting the received signal into a received data sequence as a digital signal at a prescribed sampling speed, despread the received signal by using the same code sequence as the spreading code sequence and demodulate the received signal. More specifically, the invention relates to techniques for optimizing the despreading timing for despreading the received data sequence in such a CDMA receiving apparatus and CDMA receiving method.
2. Description of the Related Art
Recent mobile radio communication systems employ direct-sequence code division multiple access (DS-CDMA) techniques whereby if the receiving electric field strength in a given frequency band drops, intended information can be recovered from another frequency band.
FIG. 1 is a block diagram schematically showing the configuration of a prior art CDMA receiver disclosed in patent document 1.
A high-frequency signal of a ratio frequency received by an antenna 11 is converted in a radio receiver 12 into a baseband signal of an intermediate frequency. The baseband signal is quadrature-detected by a quadrature detector 13 which thus outputs in-phase component (I-channel component) data and quadrature component (Q-channel component) data. The output signal of the quadrature detector 13 is band-limited by a low-pass filter (LPF) 14, and the I-channel component signal and the Q-channel component signal are each sampled at a predetermined sampling frequency, for example, chip rate, and converted into a received data sequence of digital form by an AD converter (ADC) 15. The received data sequence is then oversampled, as needed, and supplied to a path searcher 20 as well as to fingers 30a to 30d. 
Unless specifically stated otherwise, the terms “sampling speed,” “sampling frequency,” and “sampling period” used in the following description refer to the sampling speed, sampling frequency, and sampling period, respectively, of the received data sequence supplied to the path searcher 20.
The path searcher 20 includes a reference code sequence generator 21 which generates as a reference code sequence the spreading code assigned to the receiving apparatus 1, a correlation calculator 22 which calculates a correlation value indicative of correlation between the incoming received data sequence and the reference code sequence at a given timing, a power calculator 23 which calculates a correlation power value or the absolute value of the correlation value, and a timing determiner 24 which determines path timing for each path on a multipath channel. This path timing is used to determine the despreading timing for a despreader 31 in each of the fingers 30a to 30d, to be described later, to multiply the received data sequence with a despreading code for the despreading of the received data sequence.
Letting In (n=1, 2, . . . ) denote the reference code sequence of the I-channel component, Qn denote the reference code sequence of the Q-channel component, a(tn) denote the received data sequence of the I-channel component output from the AD converter 15, and b(tn) denote the received data sequence of the Q-channel component output from the AD converter 15, the correlation calculator 22 calculates the correlation value for each sampling period in accordance with the following equation (1).
[Mathematical 1]Σn{a(tn)·In+jb(tn)·Qn}(n=1,2, . . . )  (1)Likewise, the power calculator 23 calculates the correlation power value for each sampling period in accordance with the following equation (2).[Mathematical 2]Σn{[a(tn)·In]2+[b(tn)·Qn]2}(n=1,2, . . . )  (2)
The correlation calculator 22 can be realized by a matched filter MF shown in FIG. 2. In the matched filter MF, the received data sequence output from the AD converter is sequentially shifted through a shift register SFR (S0 to Sn) at the sampling frequency, while on the other hand, the reference code is held in a reference code register RSF (C0 to Cn).
The received data sequence sequentially shifted through the shift register SFR (S0 to Sn) is multiplied by multipliers (M0 to Mn) with the corresponding data in the reference code sequence held in the reference code register RSF (C0 to Cn), and the outputs of the respective multipliers (M0 to Mn) are added together by an adder A for output.
According to this matched filter MF, the correlation value between the received data sequence and the reference code sequence at a given timing can be calculated for each sampling period, and the correlation value between the received data sequence shifted in phase by one sampling period and the reference code sequence can be calculated at the next sampling time period. In this manner, all the correlation values are calculated by sequentially shifting the phase by one sampling period during one bit period of the transmitted data. According to this matched filter MF, the correlation value becomes large when the phase of the received data sequence matches that of the reference code sequence.
When a multipath direct sequence signal (DS signal) is input to the path search 20, the correlation value becomes large at the timing that matches the delay time (phase delay) of each path, and the correlation power value having a peak value proportional to the receiving electric field strength of the path is output from the power calculator 23 and supplied to the timing determiner 24.
The timing determiner 24 that received the correlation power value detects a peak value larger than a predetermined threshold value, determines for each path on the multipath channel the despreading timing at which to multiply the received data sequence with the despreading code sequence, and supplies the thus determined timing to a corresponding one of the fingers 30a to 30d. 
The fingers 30a to 30d for the respective paths are identical in configuration.
The despreader circuit 31 despreads the received code sequence input from the AD converter 15, by multiplying it with a received-data demodulating despreading code sequence at the path timing specified by the path searcher 20. A synchronous detector 32 removes the effects of fading from the detected signal by performing channel estimation. The signals detected at the respective fingers 30a to 30d are combined by a RAKE receiver 16.
Patent document 1: Japanese Unexamined Patent Publication No. 2003-198427
Patent document 2: Japanese Unexamined Patent Publication No. 2000-244367
Patent document 3: Japanese Patent No. 3322246
Patent document 4: Japanese Patent No. 3443113
As described above, the path searcher 20 detects the path timing for applying despreading. Each timing detected by the path searcher 20 represents one of discrete times corresponding to the sampling times of the received data sequence, and contains a timing error relative to the correct path timing of the incoming received signal. This timing error can become as large as one half of the sampling period.
Normally, i.e., in the presence of interference such as multipath interference or radio interference from other cells, the amount of degradation due to this timing error is not much of a problem, but in an area where reception quality is good and a high-speed data transmission can be achieved, the timing error becomes noticeable.
For example, in a case where the AD converter 15 performs the analog-to-digital conversion by oversampling the received data sequence at a rate four times the chip rate in an environment where the CQI value used in HSDPA (High Speed Downlink Packet Access) standard to measure the reception quality (SIR measurement) is about 30 which indicates the highest reception quality; in this case, if the path timing detected by the path searcher 20 is displaced from the correct path timing by one half of the sampling period, a difference of 5 dB or greater will occur compared with the case where the detected path timing coincides with the correct timing.
One possible method to minimize the timing error between the path timing detected by the path searcher 20 and the correct path timing would be to increase the oversampling rate of the received data sequence. However, since increasing the sampling speed involves increasing the amount of circuitry and greatly affects the product design, it is considered that in the current W-CDMA system, four times the chip rate is the limit.
Another possible method to minimize the timing error would be to allow the path timing by the path searcher 20 to follow the change in analog fashion by using a delay locked loop (DLL), but this would increase the complexity of the system. A technique that increases the sample rate of the AD converter 15 could be employed, but this would greatly increase the cost and power consumption.
In view of the above problems, it is an object of the apparatus and method disclosed herein to reduce, using a simple configuration, the timing error between the discrete path timing detected by the path searcher 20 and the optimum path timing determined in accordance with the actual receive time.